Sandy Bridge

Sandy Bridge is the codename for a microarchitecture developed by Intel beginning in 2005 for central processing units in computers to replace the Nehalem microarchitecture. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the Core brand.[1][2]

Sandy Bridge implementations targeted a 32 nanometer manufacturing process based on planar double-gate transistors.[3] Intel's subsequent product, codenamed Ivy Bridge, uses a 22 nanometer process. The Ivy Bridge die shrink, known in the Intel Tick-Tock model as the "tick", is based on FinFET (non-planar, "3D") tri-gate transistors. Intel demonstrated the Ivy Bridge processors in 2011.

Technology

Developed primarily by the Israel branch of Intel, the codename was originally "Gesher" (meaning "bridge" in Hebrew). The name was changed to avoid being associated with the defunct Gesher political party;[5] the decision was led by Ron Friedman, vice president of Intel managing the group at the time.[1] Intel demonstrated a Sandy Bridge processor with A1 stepping at 2 GHz during the Intel Developer Forum in September 2009.[6]

Upgraded features from Nehalem include:

    32 KB data + 32 KB instruction L1 cache (3 clocks) and 256 KB L2 cache (8 clocks) per core.
    Shared L3 cache includes the processor graphics (LGA 1155).
    64-byte cache line size.
    Two load/store operations per CPU cycle for each memory channel.
    Decoded micro-operation cache (uop cache) and enlarged, optimized branch predictor.
    Improved performance for transcendental mathematics, AES encryption (AES instruction set), and         SHA-1 hashing.
    256-bit/cycle ring bus interconnect between cores, graphics, cache and System Agent Domain.
    Advanced Vector Extensions (AVX) 256-bit instruction set with wider vectors, new extensible syntax and rich functionality.
    Intel Quick Sync Video, hardware support for video encoding and decoding.
    Up to 8 physical cores or 16 logical cores through Hyper-threading.
    Integration of the GMCH (integrated graphics and memory controller) and processor into a single die inside the processor package. In contrast, Sandy Bridge's predecessor, Clarkdale, has two separate dies (one for GMCH, one for processor) within the processor package. This tighter integration reduces memory latency even more.
    A 14- to 19-stage instruction pipeline, depending on the micro-operation cache hit or miss

Translation lookaside buffer sizes

Cache		Page Size
Name	Level	4 KB	2 MB	1 GB
DTLB	1st	64	32	4
ITLB	1st	128	8 / logical core	none
STLB	2nd	512	none	none

Performance
The average performance increase, according to IXBT Labs and Semi Accurate as well as many other benchmarking sites, at clock to clock is 11.3% compared to the Nehalem Generation, which includes Bloomfield, Clarkdale, and Lynnfield processors.
Around twice the integrated graphics performance compared to Clarkdale's (12 EUs comparison).



Cougar Point chipset flaw

On January 31, 2011, Intel issued a recall on all 67-series motherboards due to a flaw in the Cougar Point Chipset.A hardware problem, in which the chipset's SATA-II ports may fail over time, cause failure of connection to SATA-II devices, though data is not at risk. Intel claims that this problem will affect only 5% of users over 3 years, however, heavier I/O workloads can exacerbate the problem.

Intel stopped production of flawed B2 stepping chipsets and began producing B3 stepping chipsets with the silicon fix. Shipping of these new chipsets started on 14 February 2011 and Intel estimated full recovery volume in April 2011. Motherboard manufacturers (such as ASUS and Gigabyte Technology) and computer manufacturers (such as Dell and Hewlett-Packard) stopped selling products that involved the flawed chipset and offered support for affected customers. Options ranged from swapping for B3 motherboards to product refunds.

Sandy Bridge processor sales were temporarily on hold, as one cannot use the CPU without a motherboard. However, processor release dates were not affected.After two weeks, Intel continued shipping some chipsets, but manufacturers had to agree to a set of terms that will prevent customers from encountering the bug

Overclocking

With Sandy Bridge, Intel has tied the speed of every bus (USB, SATA, PCI, PCI-E, CPU cores, Uncore, memory etc.) to a single internal clock generator issuing the basic 100 MHz Base Clock (BClk).With CPUs being multiplier locked, the only way to overclock is to increase the BClk, which can be raised by only 5–7% without other hardware components failing. As a work around, Intel made available K/X-series processors, which feature unlocked multipliers; with a multiplier cap of 57 for Sandy Bridge.For the Sandy Bridge E platform, there is alternative method known as the BClk ratio overclock.

During IDF (Intel Developer Forum) 2010, Intel demonstrated an unknown Sandy Bridge CPU running stably overclocked at 4.9 GHz on air cooling

vPro remote-control (Intel Insider)

Sandy and Ivy Bridge processors with vPro capability have security features that can remotely disable a PC or erase information from hard drives. This can be useful in the case of a lost or stolen PC. The commands can be received through 3G signals, Ethernet, or Internet connections. AES encryption acceleration will be available, which can be useful for video conferencing and VoIP applications

Software development kit

With the introduction of the Sandy Bridge microarchitecture, Intel also introduced the Intel Data Plane Development Kit (Intel DPDK) to help developers of communications applications take advantage of the platform in packet processing applications, and network processors